A NAND flash memory including an electrically erasable programmable read only memory (EEPROM) has been proposed as an electrically rewritable non-volatile semiconductor memory. In the NAND flash memory, the sources and drains of memory cells arranged side by side are connected in series and the series connection of the memory cells is connected as one unit to a bit line. Furthermore, all or half of the cells arranged in the direction of a row are written into or read from simultaneously. Recently, a multi-valued memory that enables data items to be stored in one cell in a NAND flash memory has been developed.
Conventional multi-valued memory may include, for example, three memory cells or states “0”, “1”, “2” and “3”. When the memory cells are erased, the data in the memory cell is brought to state “0”. A write operation causes the threshold voltage of the memory cell to move to a higher level. When 2-bit data is stored in a single memory cell, the 2-bit data is separated into first and second page data. The first-page data and second-page data are switched using an address.
When data is written into a memory cell, the first-page data is written and then the second-page data is written. When the write data constituting the first-page or second-page data is “1”, the threshold voltage of the memory cell does not change in the write operation, with the result that the data in the memory cell remains unchanged. Namely, the data is not written. When write data constituting the first-page or second-page data is “0”, the threshold voltage of the memory cell is changed in the write operation. As a result, the data in the memory cell is changed, causing the data to be written.
It is typically assumed that the data in the memory cell in the erased state is in state “0”, i.e., the first page is “1” and the second page is “1”, resulting in “11”. First, the first-page data is written into the memory cell. When the write data is “1”, the data in the memory cell remains in state “0”. When the write data is “0”, the data in the memory cell goes to state “1”.
Next, the second-page data is written. At this time, when write data “0” is externally supplied to the memory cell whose data has become state “1” as a result of the first-page write operation, the data in the memory cell is brought into state “3” or “00”. Moreover, when data “0” is externally supplied to the memory cell whose data has remained in state “0” as a result of the first-page write operation, the data in the memory cell is brought into state “2” or “01”.
Furthermore, when data “1” is externally supplied to the memory cell whose data has become state “1” as a result of the first-page write operation, the data in the memory cell is allowed to remain in state “1” or “10”. In addition, when data “1” is externally supplied to the memory cell whose data has remained in state “0” as a result of the first-page write operation, the data in the memory cell is allowed to remain in state “0” or “11”.
During a read operation, the second-page data is read first and then the first-page data. Thus, when the second-page data is read, if the data in the memory cell is in state “0” or state “1”, the read-out data will be “1”. Furthermore, if the data in the memory cell is in state “2” or state “3”, the read-out data will be “0”. For this reason, when the second-page data is read, a determination can be made through only one operation of judging whether the data in the memory cell is in either state “1” or below or state “2” or above.
In contrast, when the first page data is read, if the data in the memory cell is in state “0” or state “2”, the data to be read will be “1”. If the data in the memory cell is in state “1” or state “3”, the data to be read will be “0”. Consequently, the first page requires a total of three read operations for the following determinations: a determination whether the data in the memory cell is in either state “0” or state “1” or above, a determination whether the data in the memory cell is in either state “1” or below or state “2”, or above, and a determination whether the data in the memory cell is in either state “2” or below or state “3”.
Thus, conventional memory devices require at least three read operations to determine the state of the data in a memory cell. Methods of programming/reading multi-bit data that attempt to address the number of reads in a conventional operation are discussed in U.S. Pat. Nos. 6,288,935 and 6,522,580. However, there continues to be a need for improved methods of programming multi-bit data into memory cells.